161 lines
6.6 KiB
C
161 lines
6.6 KiB
C
/* ====================================================================
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* Copyright (c) 1998-2011 The OpenSSL Project. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* 3. All advertising materials mentioning features or use of this
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* software must display the following acknowledgment:
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* "This product includes software developed by the OpenSSL Project
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* for use in the OpenSSL Toolkit. (http://www.openssl.org/)"
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*
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* 4. The names "OpenSSL Toolkit" and "OpenSSL Project" must not be used to
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* endorse or promote products derived from this software without
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* prior written permission. For written permission, please contact
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* openssl-core@openssl.org.
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*
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* 5. Products derived from this software may not be called "OpenSSL"
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* nor may "OpenSSL" appear in their names without prior written
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* permission of the OpenSSL Project.
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*
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* 6. Redistributions of any form whatsoever must retain the following
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* acknowledgment:
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* "This product includes software developed by the OpenSSL Project
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* for use in the OpenSSL Toolkit (http://www.openssl.org/)"
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*
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* THIS SOFTWARE IS PROVIDED BY THE OpenSSL PROJECT ``AS IS'' AND ANY
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* EXPRESSED OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE OpenSSL PROJECT OR
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* ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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* ====================================================================
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*
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* This product includes cryptographic software written by Eric Young
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* (eay@cryptsoft.com). This product includes software written by Tim
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* Hudson (tjh@cryptsoft.com). */
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#ifndef OPENSSL_HEADER_ARM_ARCH_H
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#define OPENSSL_HEADER_ARM_ARCH_H
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#include <openssl/target.h>
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// arm_arch.h contains symbols used by ARM assembly, and the C code that calls
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// it. It is included as a public header to simplify the build, but is not
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// intended for external use.
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#if defined(OPENSSL_ARM) || defined(OPENSSL_AARCH64)
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// ARMV7_NEON is true when a NEON unit is present in the current CPU.
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#define ARMV7_NEON (1 << 0)
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// ARMV8_AES indicates support for hardware AES instructions.
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#define ARMV8_AES (1 << 2)
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// ARMV8_SHA1 indicates support for hardware SHA-1 instructions.
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#define ARMV8_SHA1 (1 << 3)
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// ARMV8_SHA256 indicates support for hardware SHA-256 instructions.
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#define ARMV8_SHA256 (1 << 4)
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// ARMV8_PMULL indicates support for carryless multiplication.
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#define ARMV8_PMULL (1 << 5)
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// ARMV8_SHA512 indicates support for hardware SHA-512 instructions.
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#define ARMV8_SHA512 (1 << 6)
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// ARMV8_SHA3 indicates support for hardware SHA-3 instructions including EOR3.
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#define ARMV8_SHA3 (1 << 11)
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// Combination of all Armv8 Neon extension bits: 0x087c
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// NOTE: If you add further Armv8 Neon extension bits, adjust
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// "Test algorithm dispatch without CPU indicator or Neon extension capability bits"
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// in util/all_tests.json
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// The Neoverse N1, V1, V2, and Apple M1 micro-architectures are detected to
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// allow selecting the fasted implementations for SHA3/SHAKE and AES-GCM.
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// Combination of all CPU indicator bits: 0x7080
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// NOTE: If you add further CPU indicator bits, adjust
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// "Test algorithm dispatch without CPU indicator bits" in util/all_tests.json.
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#define ARMV8_NEOVERSE_N1 (1 << 7)
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#define ARMV8_NEOVERSE_V1 (1 << 12)
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#define ARMV8_APPLE_M (1 << 13)
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#define ARMV8_NEOVERSE_V2 (1 << 14)
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// Combination of CPU indicator bits and Armv8 Neon extension bits: 0x78fc
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// ARMV8_DIT indicates support for the Data-Independent Timing (DIT) flag.
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#define ARMV8_DIT (1 << 15)
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// ARMV8_DIT_ALLOWED is a run-time en/disabler for the Data-Independent
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// Timing (DIT) flag capability. It makes the DIT capability allowed when it is
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// first discovered in |OPENSSL_cpuid_setup|. But that bit position in
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// |OPENSSL_armcap_P| can be toggled off and back on at run-time via
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// |armv8_disable_dit| and |armv8_enable_dit|, respectively.
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#define ARMV8_DIT_ALLOWED (1 << 16)
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// ARMV8_RNG indicates supports for hardware RNG instruction RNDR.
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#define ARMV8_RNG (1 << 17)
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//
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// MIDR_EL1 system register
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//
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// 63___ _ ___32_31___ _ ___24_23_____20_19_____16_15__ _ __4_3_______0
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// | | | | | | |
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// |RES0 | Implementer | Variant | Arch | PartNum |Revision|
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// |____ _ _____|_____ _ _____|_________|_______ _|____ _ ___|________|
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//
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# define ARM_CPU_IMP_ARM 0x41
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# define ARM_CPU_PART_CORTEX_A72 0xD08
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# define ARM_CPU_PART_N1 0xD0C
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# define ARM_CPU_PART_V1 0xD40
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# define ARM_CPU_PART_V2 0xD4F
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# define MIDR_PARTNUM_SHIFT 4
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# define MIDR_PARTNUM_MASK (0xfffUL << MIDR_PARTNUM_SHIFT)
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# define MIDR_PARTNUM(midr) \
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(((midr) & MIDR_PARTNUM_MASK) >> MIDR_PARTNUM_SHIFT)
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# define MIDR_IMPLEMENTER_SHIFT 24
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# define MIDR_IMPLEMENTER_MASK (0xffUL << MIDR_IMPLEMENTER_SHIFT)
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# define MIDR_IMPLEMENTER(midr) \
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(((midr) & MIDR_IMPLEMENTER_MASK) >> MIDR_IMPLEMENTER_SHIFT)
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# define MIDR_ARCHITECTURE_SHIFT 16
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# define MIDR_ARCHITECTURE_MASK (0xfUL << MIDR_ARCHITECTURE_SHIFT)
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# define MIDR_ARCHITECTURE(midr) \
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(((midr) & MIDR_ARCHITECTURE_MASK) >> MIDR_ARCHITECTURE_SHIFT)
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# define MIDR_CPU_MODEL_MASK \
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(MIDR_IMPLEMENTER_MASK | \
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MIDR_PARTNUM_MASK | \
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MIDR_ARCHITECTURE_MASK)
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# define MIDR_CPU_MODEL(imp, partnum) \
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(((imp) << MIDR_IMPLEMENTER_SHIFT) | \
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(0xfUL << MIDR_ARCHITECTURE_SHIFT) | \
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((partnum) << MIDR_PARTNUM_SHIFT))
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# define MIDR_IS_CPU_MODEL(midr, imp, partnum) \
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(((midr) & MIDR_CPU_MODEL_MASK) == MIDR_CPU_MODEL(imp, partnum))
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#endif // ARM || AARCH64
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#endif // OPENSSL_HEADER_ARM_ARCH_H
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