make fully stateful in module gene.
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@@ -8,5 +8,5 @@ class BaseNodeGene(BaseGene):
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def __init__(self):
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super().__init__()
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def forward(self, attrs, inputs, is_output_node=False):
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def forward(self, state, attrs, inputs, is_output_node=False):
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raise NotImplementedError
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